Volatile memory circuits are quite common today. Such memory circuits can be contained in an individual integrated circuit (IC) chip or can be part of other IC's. These IC's include a configurable IC that uses a memory circuit to store configuration data. The configurable IC can be configured to perform a set of operations based on the stored configuration data.
The use of configurable IC's has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (FPGA). An FPGA is a field programmable IC that has an internal array of logic circuits (also called logic blocks) that are connected together through numerous interconnect circuits (also called interconnects) and that are surrounded by input/output blocks. Like some other configurable IC's, the logic circuits and the interconnect circuits of an FPGA are configurable. In other words, each of these circuits receives configuration data that configures the circuit to perform an operation in a set of operations that it can perform. One benefit of configurable IC's is that they can be uniformly mass produced and then subsequently configured to perform different operations.
As mentioned above, configurable IC's typically store their configuration data in memory cells. FIG. 1 illustrates a memory circuit 100 of a configurable IC. As shown in this figure, the memory circuit 100 includes: (1) a storage cell 128 for storing a configuration data value; (2) a VDDcell line 106 for supplying power to the storage cell 128; (3) true and complement bit lines 110 and 115 for reading and/or writing the contents of the storage cell 128; (4) pass gates 120 and 125 for connecting the bit lines 110 and 115 to the storage cell 128; and (5) output lines 160 and 165 for outputting, through configuration buffers 140 and 145, the contents of the storage cell 128 without the need for a read operation.
The typical storage cell 128 in the art requires that the voltage within the cell 128 and through the buffers 140 and 145 be driven to the rails in order for the cell 128 to retain stable values and output a useable configuration value (i.e., VDDcell 106 is typically VDD). If the voltage within the storage cell 128 is less than the voltage on a word line used to read the cell, then a read operation could cause instability in the value stored by the storage cell 128 by undesirably altering the value stored in the storage cell 128. This condition is also known as “read upset.”
However, requiring the voltage within the cell 128 and through the buffers 140 and 145 to be driven to the rails exasperates current leakage from the cell, since current leakage from the memory cell is non linearly (e.g., exponentially) proportional to the voltages that are used to store data in the memory cell. Specifically, in the memory cell 100 there are two kinds of leakage that are problematic: sub threshold leakage and gate leakage.
FIG. 2 illustrates an example of sub threshold leakage through an NMOS transistor 200 that is commonly used in memory circuits. In FIG. 2, the gate and source leads of the NMOS transistor 200 are short circuited to represent that their voltage difference is zero (i.e., Vg−s=0). Even though the transistor is “off” in this sub threshold condition, there is still undesirable leakage current through the transistor 200, as shown in FIG. 2.
FIG. 3 illustrates an example of gate leakage through an NMOS transistor 305. Electron tunneling through the gate oxide of a transistor causes gate leakage current. For a 90 nm electronic component (e.g., a transistor), gate oxide can be about fourteen angstroms or approximately seven silicon dioxide atoms thick. This distance is sufficiently short to allow tunneling current to flow through the gate oxide even at voltage levels as low as one volt. Gate leakage in N-channel devices is significantly worse than in P-channel devices.
With the size of electronic components continually becoming smaller due to improvements in semiconductor technology, leakage current is a continually growing problem. Leakage current in a standard (six transistor) memory cell is exponentially proportionate to voltage. So if the voltage in the cell can be reduced, then the amount of leakage (i.e., both gate and sub threshold leakage) in the cell can be exponentially reduced. However, a typical memory cell has particular voltage requirements in order for the cell to function properly. Thus, if the voltage within the cell is reduced too much, then the cell becomes unstable and unable to store and output data reliably, as seen in the case of the read upset condition. Thus, there is a need in the art for a useable reduced power configuration storage cell, such that the leakage from electronic components within the cell is reduced, while retaining useable output configuration signals.